1. Display Interface Introduction

SPI Interface

SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous serial communication bus commonly used for short-distance communication between an MCU and peripherals. Standard SPI consists of 4 signal lines: SCLK (clock), MOSI (master output, slave input), MISO (master input, slave output), and CS (chip select).

Differences from standard SPI:

• Display SPI usually omits MISO (the screen does not need to return data), keeping only the unidirectional MOSI transfer and adding a D/C (command/data select) line to distinguish transfer types — 5 lines in practice (CS, SCLK, MOSI, D/C);
• The communication direction changes from full-duplex to simplex (write-only), which better fits display use cases;
• Data frames must distinguish command bytes from pixel data bytes with the help of D/C, whereas ordinary SPI peripherals usually do not make this distinction;
• The clock rate typically runs at 20~80 MHz to meet display refresh bandwidth requirements.

QSPI Interface

QSPI (Quad Serial Peripheral Interface) is an interface form that extends standard SPI with 4 data lines (IO0~IO3). The 4 lines can transmit 4 bits of data in parallel simultaneously, giving a theoretical bandwidth of 4× standard SPI. Signal lines include: CS, SCLK, IO0, IO1, IO2, IO3 — 6 lines in total.

Differences from ordinary QSPI:

• Ordinary QSPI is mainly intended for Flash memory reads, where the command/address/data phases can all use four lines;
• Display QSPI usually adopts a hybrid mode of "single-line commands + four-line data": the command phase runs on a single line (IO0), while the pixel data phase switches to four-line parallel transfer;
• Display QSPI focuses on high-speed refresh of display data (register 0x2C writes), whereas ordinary QSPI emphasizes random address reads;
• The data direction is mostly writes with few read-back needs, while ordinary QSPI requires bidirectional support.

8080 Interface

The 8080 interface (Intel 8080 timing) is a parallel bus interface, available in two specifications: 8080-8 (8-bit data bus) and 8080-16 (16-bit data bus). Signal lines include: CS, WR (write strobe), RD (read strobe), D/C (command/data), and a D0~D7 or D0~D15 data bus.

Differences from ordinary QSPI:

• 8080 is a parallel interface, while QSPI is serial;
• 8080 transfers 8 or 16 bits at a time, while QSPI transfers 4 bits per clock cycle — 8080 achieves high bandwidth even at low clock rates;
• 8080 uses many pins (8/16 data lines + control lines), while QSPI needs only 6 lines;
• 8080 timing is simple with low MCU timing requirements, while QSPI places higher demands on timing and protocol switching;
• 8080 suits applications with abundant pin resources and high refresh-rate requirements; QSPI suits applications with limited pins but moderate bandwidth requirements.

Interface Comparison

Item	SPI	QSPI	8080
Number of Signal Lines	5 (CS, SCLK, MOSI, MISO, D/C)	6 (CS, SCLK, IO0~IO3)	11~19 (CS, WR, RD, D/C, D0~D7/15)
Data Width	1 bit/cycle	4 bits/cycle	8 or 16 bits/cycle
Transfer Mode	Serial simplex	Serial four-line parallel	Parallel
Typical Clock	20~80 MHz	20~80 MHz	10~50 MHz
Max Clock Accepted by TR2S	100MHz	100 MHz	50 MHz
Pin Usage	Few	Fewer	Many
Refresh Bandwidth	Low	Medium	High
Applicable Scenarios	Limited pins, low refresh rate	Limited pins, medium refresh rate	Abundant pins, high refresh rate